In general, two distinct stud metallurgical technologies are known in the semiconductor fabrication industry. One technology involves depositing a layer of doped glass such as borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) on a processed substrate, etching vias through the doped glass layer so as to expose selected structures on the substrate, and filling these vias with metal to define conductive studs that interconnect the underlying structures through the overlying metal. The other technology involves depositing a metal layer directly on the processed substrate, patterning the metal to define the conductive studs, depositing the doped glass layer, and planarizing the glass layer to expose the upper surfaces of the conductive studs.
As the density of integrated circuits increases, the space taken up by a metal line plus the spacing between lines decreases (in the art, this is referred to as a "tight" metal pitch). Both of the above-mentioned stud metallization techniques become more difficult to implement at a tighter metal pitch. These difficulties are illustrated in FIGS. 1 and 2 (Prior Art). As shown in FIG. 1, when vias 2 are formed in a layer of doped glass 4 deposited on a substrate 1 prior to metal deposition, the high metal pitch necessitates the use of vias having vertical sidewall slopes. Moreover, the width of the vias must decrease. The resulting vias have a high "aspect ratio" (i.e., the ratio of the depth to the width W of the via), As is well known in the art, it is very difficult to deposit a layer of metal within a via having a high aspect ratio without forming voids in the metal and, hence, decreasing the conductivity/reliability of the metal within the via. This the so-called "metal hole-fill" problem. As shown in FIG. 2, a similar aspect ratio problem is presented when the doped glass layer is to be deposited on a substrate 1 having closely spaced conductive studs 6 disposed thereon. Again, it will be difficult to deposit a void-free doped glass in the high aspect ratio "gap" between the two studs 6. This is the so-called "insulator gap-fill" problem.
In the prior art, the metal hole-fill problem has been addressed by chamfering the vertical via sidewalls prior to metal deposition. See, e.g. U.S. Pat. No. 4,595,452, entitled, "Method And Apparatus For Plasma Etching," issued June 17, 1986 to Landau et al and assigned to Oerlikon-Buhrle U.S.A. However, for various reasons (e.g., maintenance of device planarity) it would be advantageous to utilize the metallization technology in which the studs are defined prior to insulator deposition. Simply chamfering the metal studs prior to insulator deposition is not a satisfactory solution to the insulator gap-fill problem in that the attendant change in the metal profile may substantially degrade its conductivity characteristics.
Accordingly, a need exists in the art for a metallization process that addresses the insulator gap-fill problem without etching the metal after stud definition.